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MAX17710
Energy-Harvesting Charger and Protector
The LDO becomes active when the AE pin is pulsed
above or held above its logic-high threshold, but the
regulator output is not immediately enabled. The device
first charges the external capacitor on PCKP. When the
voltage level on PCKP reaches 3.7V, the regulator output
is enabled in high-current mode. Powering the LDO from
PCKP instead of directly from the cell allows the device
to support large surge or startup inrush currents from the
load that the cell would be unable to handle directly.
Once in high-current mode, the AE pin can remain logic-
high or transition to an open state, and the ouput remains
active. The LDO returns to shutdown only when the AE
pin is driven below its logic-low threshold. Alternatively,
the LDO is transitioned to low-current mode by pulsing
or holding the LCE to the REG pin voltage, followed by
pulsing or holding the AE pin logic-low. Note that the
regulator transitions through a state where both high-
current and low-current modes are active at the same
time. While in low-current mode, the quiescent current
drain of the cell is reduced to 150nA, while the maximum
load current able to be supplied becomes 50 F A. Similar
to the AE pin operation, the regulator remains active if the
SHUTDOWN
PCKP OFF
LCE pin is open or pulled to REG, and returns to shutdown
mode when LCE is driven below its logic-low threshold.
Figure 5 is the regulator output state diagram.
Cell Undervoltage Lockout (UVLO)
If the cell and PCKP capacitance cannot provide sus-
tained support for the load, then the voltage at PCKP col-
lapses. When PCKP collapses, the system load typically
stops and allows the PCKP voltage to recover, resulting
in a perpetual retry in a futile attempt to support a load
that cannot be supported. When PCKP fails in this way,
the device shuts off the REG output to prevent futile load
retries and protect the cell from overdischarge. When the
REG output is latched off, the BATT quiescent current
reduces to 1nA (typ). Once UVLO occurs, the regulator
output remains disabled until the device detects that a
charge source has been connected to the system (V CHG
> 4.15V). Figure 6 shows the UVLO protection modes.
Connecting any load to REG or PCKP instead of connect-
ing directly to the cell is highly recommended. This con-
trols the quiescent current during shutdown, enables the
device to support startup during cold, and also protects
the cell from overdischarge.
LCE PULSED LOW
REG OFF
I QBATT = 1nA (typ)
AE PULSED HIGH
AE PULSED LOW
CHARGE
DETECTED
VCHG > VCE
STARTUP
PCKP ON
REG OFF
I QBATT = PCKP CAPACITOR
CHARGE CURRENT
+ 725nA (typ)
STARTUP
SUCCESS
V PCKP > 3.7V
AE REGULATOR
ACTIVE
PCKP ON
REG ON
I QBATT = 725nA (typ)
LCE PULSED
HIGH
LCE PULSED
LOW
AE AND LCE
REGULATORS ACTIVE
PCKP ON
REG ON
I QBATT = 875nA (typ)
AE PULSED
LOW
AE PULSED
HIGH
LCE REGULATOR
ACTIVE
PCKP ON
REG ON
I QBATT = 150nA (typ)
STARTUP FAIL
V PCKP < 2.15V
AFTER 5s
UNDERVOLTAGE
LOCKOUT
PCKP OFF
REG OFF
I QBATT = 1nA (typ)
POWER-ON RESET (POR)
Figure 5. Regulator Output State Diagram
Maxim Integrated
CELL UNDERVOLTAGE
V PCKP < 2.15V (HIGH-CURRENT MODE)
V PCKP < 3.0V (LOW-CURRENT MODE)
AFTER 500μs
13
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